Senior Engineer - FPGA Verification

• FPGA Verification
• SystemVerilog
• UVM
• ASIC Verification
• Hardware Validation

Define and execute verification strategies for FPGA and ASIC designs supporting advanced 5G and 6G radio and RAN compute products. Develop and maintain UVM-based verification environments, testbenches, and regression suites using SystemVerilog and industry-standard simulators. Analyze simulation results, debug complex issues, and collaborate closely with hardware, software, and system teams to ensure functional correctness and high-quality delivery. Drive coverage closure, contribute to continuous improvement of verification processes and tools, produce clear documentation, and mentor junior engineers in a collaborative, agile environment.