DFT Staff Engineer

• DFT Architecture
• Scan Insertion
• ATPG
• Memory BIST
• Logic BIST
• JTAG
• Boundary Scan
• Compression
• SoC DFT
• Verilog
• Synopsys DFT Compiler
• Tessent
• Scripting (Tcl/Perl/Python)
• Timing Analysis

As a DFT Staff Engineer at Broadcom, you will lead the design and implementation of Design-for-Test architectures for advanced semiconductor products. You will be responsible for developing DFT strategies encompassing scan chain insertion, compression, ATPG, memory BIST, logic BIST, and JTAG/IEEE 1149.1 boundary scan at both IP and SoC levels. Your role involves collaborating with front-end design teams to integrate DFT structures early in the design cycle, ensuring optimal test coverage while minimizing area and timing impact. You will drive DFT methodology improvements, define best practices, and mentor junior engineers. Additionally, you will work with test and manufacturing teams to ensure silicon testability goals are met and support yield analysis and debug activities.