IO Design Architecture Expert

• PCIe
• PCI-X
• CXL
• IO Bridge Architecture
• Chip-Level Design
• SoC Design
• MSI/LSI Interrupt Mechanisms
• TCEs
• DMA Ordering
• MMIO Address Mapping
• Address Translation Services (ATS)
• Micro-Architecture
• Interface Design
• Server-Class Processors
• Hardware Architecture

You will serve as an IO Design Architecture Expert responsible for defining, developing, and documenting chip-level architecture for high-performance IO bridges, such as PCIe bridges, within server-class processor designs. This is a senior technical role requiring deep expertise in IO subsystem architecture.

Key responsibilities include architecting and specifying IO subsystem components with a focus on PCIe and other server-grade IO bridges. You will develop detailed architectural descriptions, interface definitions, and micro-architecture guidance for implementation teams. Collaboration with cross-functional teams is essential to ensure architectural integrity and compliance with industry standards.

The role demands a strong understanding of major IO and interconnect standards including PCIe, PCI-X, CXL, and related protocols. Proficiency is required in MSI and LSI interrupt mechanisms, Translation Control Entries (TCEs), DMA ordering rules and transaction flows, MMIO address mapping and access semantics, and Address Translation Services (ATS) with related coherency and translation features. You must be able to translate architectural requirements into clear specifications used by design, verification, and firmware teams. Proven experience in server-class SoC or IO subsystem design is highly desirable.