Senior Lead RTL Design (FEINT) Engineer ⭐ Featured

• ASIC Synthesis
• Timing Closure
• CDC
• Lint
• DFX
• ECO Implementation
• Synthesis Constraints
• Low-power Design

This role focuses on front-end implementation including synthesis, timing closure, CDC, lint, and DFX for high-speed processor designs. You will define synthesis constraints, analyze timing and power issues, and drive ECO implementations. The position requires close collaboration with RTL teams to resolve timing and quality issues. You will also evaluate tools and refine methodologies for low-power and high-performance designs. Strong ASIC synthesis and STA expertise is required.